I’ve been working in processor and embedded systems simulation for my whole career, as a simulator developer and as a user of simulation for firmware development.

System simulation is more than just simulators. It’s an ecosystem of tooling and frameworks that tie a specification through to a simulation to a verification of the system under test. The categories below reflect that ecosystem. Standards and interoperability (FMI/FMU, TLM, IP-XACT) cross-cut all of them.

graph LR
    %% Pipeline flow (top to bottom, displayed as left column)
    subgraph pipeline["Activity Pipeline"]
        direction TB
        p1([Specify]) --> p2([Simulate]) --> p3([Verify]) --> p4([Integrate])
    end

    %% Section hierarchy (top to bottom, displayed as right column)
    subgraph sections["Page Sections"]
        direction TB
        spec[Machine Readable
Specifications]
        spec --> reg[Register and Device
Descriptions]
        spec --> isa[ISA Specifications]
        spec --> sysarch[System Architecture]
        spec --> iface[Interface Definitions]
        spec --> cosim[Co-simulation Interfaces]

        sim[System Simulation]
        sim --> proc[Simulated Processors]
        sim --> fw[Frameworks and Kernels]
        fw --> hyp[Hypervisors and
Partitioning]
        sim --> plant[Plant and Physical
Modelling]
        sim --> fed[Federated and Distributed
Simulation]

        test[Testing and Stimulus]
        test --> tb[Testbenches and
Verification]
        test --> hil[Hardware-in-the-Loop]
        sim -.-> tb

        build[Build and Integration]
        build --> buildsys[Build Systems]
        build --> mw[Middleware and Transport]
        build --> codegen[Code Generation]
        build --> ci[CI for Simulation]
        build --> repro[Reproducibility]
    end

    %% Map sections to pipeline stages
    p1 -.-> spec
    p2 -.-> sim
    p3 -.-> test
    p4 -.-> build

    click spec "#machine-readable-system-specifications" "Exchange formats, DSLs, ISA specs"
    click reg "#register-and-device-descriptions" "SVD, SystemRDL, IP-XACT, Device Tree"
    click isa "#isa-specifications" "ARM XML, RISC-V opcodes, Sail"
    click sysarch "#system-architecture" "SysML v2, AADL"
    click iface "#interface-definitions" "IDL, Protobuf, OpenAPI, ASN.1"
    click cosim "#co-simulation-interfaces" "FMI"
    click sim "#system-simulation" "Processors, frameworks, plant, federated"
    click proc "#simulated-processors" "ISS, virtual platforms, RTL simulation"
    click fw "#frameworks-and-kernels" "SystemC, logic sim, tracing, RTOS, hypervisors"
    click hyp "#hypervisors-and-partitioning" "Jailhouse"
    click plant "#plant-and-physical-modelling" "Modelica, FMI/FMU, physics"
    click fed "#federated-and-distributed-simulation" "HLA, DIS, DDS, automotive, robotics"
    click test "#testing-and-stimulus" "Testbenches, verification, HIL"
    click tb "#testbenches-and-verification" "UVM, cocotb, embedded test frameworks"
    click hil "#hardware-in-the-loop" "HIL platforms, debug probes, bus adapters"
    click build "#build-and-integration" "Build systems, code gen, CI, reproducibility"
    click buildsys "#build-systems" "Yocto, Buildroot, KAS, FuseSoC"
    click mw "#middleware-and-transport" "DDS, Zenoh, iceoryx"
    click codegen "#code-generation" "Jinja2, svd2rust, PeakRDL, rggen"
    click ci "#ci-for-simulation" "GitHub Actions, Renode, Docker"
    click repro "#reproducibility" "Nix, Docker, Yocto"

    style p1 fill:#f9f,stroke:#333
    style p2 fill:#bbf,stroke:#333
    style p3 fill:#bfb,stroke:#333
    style p4 fill:#fbf,stroke:#333
    style spec fill:#f9f,stroke:#333
    style sim fill:#bbf,stroke:#333
    style test fill:#bfb,stroke:#333
    style build fill:#fbf,stroke:#333

Machine Readable System Specifications

Formal descriptions of hardware and system interfaces. These serve as the input stage of a code generation pipeline: specification → parser → template → generated output (article forthcoming).

Register and Device Descriptions

Tool Type Description
CMSIS-SVD Standard Schema ARM/RISC-V peripheral register descriptions in XML. Widely supported by tooling.
SystemRDL Standard DSL Accellera register and address map specification language.
IP-XACT (IEEE 1685) Standard Schema IP component packaging and system integration metadata in XML. Free via IEEE GET.
Device Tree Standard Schema Hardware description format for Linux kernel and bootloader device drivers.

ISA Specifications

Machine readable instruction set architecture data — instructions, encodings, system registers, and formal models.

ARM

Tool Type Description
ARM A-profile XML ISA Formal Spec System registers, AArch64/AArch32 instruction encodings, decode trees. XML archives.
MRA Tools OSS Tool Scripts for processing ARM XML specs. ASL transpiler to C, Verilog, SMT. Blog.

RISC-V

Tool Type Description
riscv-opcodes OSS ISA Data Official RISC-V instruction opcode definitions. Easy to parse text format.
Sail RISC-V ISA Formal Spec Official formal ISA model in Sail language. Behavioural spec for verification and synthesis.
riscv-config OSS Tool RISC-V configuration spec for compliance. Describes implemented features in YAML.
riscv-isa-data OSS ISA Data YAML: opcodes, CSRs, extensions. Overview.

System Architecture

Tool Type Description
SysML v2 Standard DSL OMG systems modelling language. Textual notation in v2.
AADL Standard DSL SAE architecture analysis and design language for real-time embedded systems.
SysPhS (OMG) Standard DSL SysML extension for physical interaction and signal flow simulation. Translates to Modelica and Simulink/Simscape.

Interface Definitions

Tool Type Description
OMG IDL Standard DSL Interface definition language for CORBA and DDS distributed systems.
Protocol Buffers OSS Tool Google’s language-neutral serialization format with code generation via protoc.
OpenAPI Standard Schema REST API descriptions in YAML/JSON. Drives client/server code generation.
ASN.1 Standard DSL ITU-T notation for defining data structures in telecom and aerospace.

Co-simulation Interfaces

Tool Type Description
FMI (v2.0, v3.0) Standard Protocol Functional Mock-up Interface for model exchange and co-simulation.
FMI Library OSS Library Modelon C library for loading and interacting with FMUs.

System Simulation

Simulated Processors

The spectrum from instruction-level interpretation through cycle-accurate RTL simulation. Higher fidelity costs more simulation time.

Instruction Set Simulators

Tool Type Description
QEMU OSS Tool Fast processor emulator with KVM acceleration. ARM, RISC-V, x86 and more.
Renode OSS Tool Embedded systems simulation framework by Antmicro. Multi-node, multi-arch.
gem5 OSS Tool Cycle-accurate simulator for computer architecture research.
RISC-V Spike OSS Tool RISC-V ISA reference functional simulator.
Imperas OVP Free / Commercial Open Virtual Platforms for multi-core instruction-accurate simulation.

Vendor Virtual Platforms

Tool Type Description
ARM Fast Models Commercial IP SystemC TLM-based models for ARM Cortex-A/R/M processors.
Synopsys Virtualizer / Simics Commercial Tool Full-system virtual prototyping. Simics acquired from Wind River.
Cadence VLAB Commercial Tool Virtual platform simulation environment.

RTL Simulation

Tool Type Description
Verilator OSS Tool Fast Verilog/SystemVerilog to C++/SystemC compiler. Lint, coverage, assertions.
Icarus Verilog OSS Tool Verilog simulation and synthesis tool.
Siemens Questa (formerly ModelSim) Commercial Tool SystemVerilog/VHDL simulation and verification. Free Starter Edition via Intel/Altera Quartus.
Synopsys VCS Commercial Tool Industry-standard SystemVerilog simulator.
Cadence Xcelium Commercial Tool Multi-language (Verilog, VHDL, SystemC) parallel simulation.

FPGA prototyping platforms (Cadence Palladium, Synopsys ZeBu) bridge RTL simulation and physical hardware but are outside the scope of this page.

Frameworks and Kernels

Simulation engines, verification frameworks, and the RTOS layers that run on them. See SystemC below for detailed coverage.

System Simulation

Tool Type Description
SystemC / TLM 2.0 (IEEE 1666) Standard API C++ class library standard for system-level modelling. Free via IEEE GET. See detailed section.
Accellera SystemC OSS Library Reference implementation of IEEE 1666. Apache 2.0. The only full open source implementation.
Renode OSS Tool Also a framework: C#/Python peripheral modelling API, Robot Framework integration.
VCML OSS Library Virtual Components Modelling Library. SystemC/TLM convenience layer by MachineWare.
SCML Commercial Library Synopsys SystemC Modelling Library. TLM 2.0 convenience layer for Virtualizer peripheral models.
CCI Standard API Accellera SystemC Configuration, Control and Inspection. Standardizes model configuration; register introspection on roadmap.
Accellera CCI OSS Library Reference implementation of CCI standard. Apache 2.0.

Logic Simulation and Verification

Tool Type Description
cocotb OSS Library Python coroutines driving HDL simulation. Works with Verilator, Icarus, VCS, Questa.
cocotb-bus OSS Library Bus protocol drivers (AXI, Avalon, Wishbone) for cocotb testbenches.
UVM (IEEE 1800.2) Standard Methodology Universal Verification Methodology for SystemVerilog testbenches. Free via IEEE GET.
Accellera UVM OSS Library Reference implementation of UVM. SystemVerilog class library.
UVM-SystemC OSS Library UVM ported to SystemC/C++. Enables UVM methodology without SystemVerilog.
Verilator OSS Tool Also a framework: C++ testbench API, SystemC integration, VCD/FST tracing.

Tracing and Debugging

Tool Type Description
VCD Format IEEE 1364 Value Change Dump. Standard signal-level trace format. Text-based, widely supported.
FST Format Fast Signal Trace. GTKWave’s binary alternative to VCD. Smaller files, faster load.
srzip Format sigrok native format. ZIP-based container with metadata and binary samples.
GTKWave OSS Tool Waveform viewer for VCD, FST, and other trace formats.
Surfer OSS Tool Extensible waveform viewer. VCD, FST, GHW support. Modern GTKWave alternative.
sigrok OSS Tool Signal analysis suite. Supports 100+ logic analyzer hardware devices.
PulseView OSS Tool sigrok GUI. Protocol decoders, logic analyzer capture and analysis.
Lauterbach TRACE32 Commercial Tool Debug and trace tools for embedded processors. Hardware trace support.

RTOS with Simulation Support

These RTOS are listed for their host-compiled simulation targets and CI integration, not as a general RTOS survey.

Tool Type Description
Zephyr (native_sim) OSS Tool POSIX-based host simulation board. Runs Zephyr apps natively for CI with Twister.
FreeRTOS OSS Library POSIX port enables host-compiled testing. Widely used in MCU firmware.
NuttX OSS Tool POSIX-compliant RTOS. sim board runs on host; QEMU targets for ARM/RISC-V CI.

Hypervisors and Partitioning

Tool Type Description
Jailhouse OSS Tool Linux-based partitioning hypervisor by Siemens. Static partitioning of CPU cores, memory, and I/O into isolated cells running bare-metal or RTOS inmates. QEMU target for development.

Plant and Physical Modelling

Continuous-time and multi-domain physical models — the “world outside the chip.”

Modelica Ecosystem

Tool Type Description
OpenModelica OSS Tool Modelica-based modelling and simulation environment for multi-physics systems.
Modelica Standard Library OSS Library Electrical, mechanical, thermal, fluid component models.
VehicleInterfaces OSS Library Standardized interfaces for automotive subsystem modelling.

FMI / FMU

Tool Type Description
FMI (v2.0, v3.0) Standard Protocol Functional Mock-up Interface for model exchange and co-simulation.
FMI Library OSS Library Modelon C library for loading and interacting with FMUs.
FMI-LS-BUS Standard Protocol FMI layered standard for network communication (CAN, LIN, FlexRay).
Reference-FMUs OSS Library Standardized FMU test models with fmusim command-line runner.
FMPy OSS Library Python library for simulating FMUs. GUI and command-line interface.

Physics Simulation

Tool Type Description
Gazebo OSS Tool Physics simulation for robotics. ROS 2 integration.
Simulink / Simscape Commercial Tool MathWorks model-based design. Industry standard for control systems.
Scilab / Xcos OSS Tool Numerical computation with graphical block diagram editor (Simulink-like).
GNU Octave OSS Tool MATLAB-compatible numerical computing with control systems toolbox.

Federated and Distributed Simulation

Connecting multiple simulators into a coherent system-of-systems.

Automotive and Robotics

Tool Type Description
ROS 2 OSS Tool Robot Operating System. DDS-based middleware for multi-process simulation and deployment.
Gazebo OSS Tool Pairs with ROS 2 for physics-in-the-loop robotics simulation.
PX4 SITL OSS Tool Software-in-the-loop for PX4 autopilot. Gazebo and jMAVSim backends.
CARLA OSS Tool Open-source autonomous driving simulator. Unreal Engine based.

QEMU Co-simulation

Tool Type Description
VPSim OSS Tool CEA-List virtual platform framework. QEMU + SystemC integration.
QBox / libqbox OSS Library Qualcomm/GreenSocs QEMU-in-SystemC for heterogeneous SoC simulation.
Xilinx Remote Port OSS Tool Co-simulation bridge in Xilinx QEMU fork. Connects QEMU to SystemC/Verilator processes.

Standards

Standard Type Description
HLA (IEEE 1516) Standard Protocol High Level Architecture for defence and large-scale distributed simulation.
NASA TrickHLA OSS Library NASA open-source HLA implementation for the Trick simulation environment.
DIS (IEEE 1278) Standard Protocol Distributed Interactive Simulation. Real-time protocol for military training.
Open-DIS OSS Library Open-source DIS implementations (Java, C++, Python, JS). Tutorial.
DDS (OMG) Standard Protocol Data Distribution Service. Publish-subscribe middleware for real-time systems.
DCP Standard Protocol Distributed Co-Simulation Protocol. Modelica Association standard for integrating models and real-time systems via UDP/TCP.
FSS Standard Protocol Accellera Federated Simulation Standard. Interoperability across simulation standards and tools (in development).
FMI-LS-BUS Standard Protocol FMI layered standard for network communication (CAN, LIN, FlexRay) in co-simulation.
ECSS SMP Standard API European space industry Simulation Model Portability standard.
EUROCAE ED-247 Standard Protocol Avionics simulation interface standard for virtual integration.
SISO WebLVC Standard Protocol Web-based Live, Virtual, Constructive simulation interoperability.

Testing and Stimulus

Testbenches and Verification

HDL Verification

Tool Type Description
UVM (IEEE 1800.2) Standard Methodology Universal Verification Methodology for constrained-random, coverage-driven SystemVerilog testbenches. Free via IEEE GET.
Accellera UVM OSS Library Reference implementation of UVM. SystemVerilog class library.
cocotb OSS Library Python coroutine-based HDL testbenches. CI-friendly alternative to SystemVerilog UVM.
cocotb-bus OSS Library Reusable bus protocol drivers (AXI, Avalon, Wishbone) for cocotb.
pyuvm OSS Library Python implementation of UVM. Runs on cocotb simulators.

Embedded Test Frameworks

Tool Type Description
Robot Framework OSS Tool Keyword-driven test automation. Renode integration for embedded system-level tests.
Zephyr Twister OSS Tool Zephyr’s test runner. Manages native_sim, QEMU, and hardware targets from CI.
Unity / Ceedling OSS Tool Unit testing and build automation for embedded C. CMock for test doubles.

On-Target and Debugger-Based Testing

Tool Type Description
metal.test OSS Tool Debugger-based bare-metal testing via GDB Python. No test harness on target.
iSYSTEM testIDEA Commercial Tool Unit testing on real hardware via debug probes. No target-side instrumentation.

Methodology

Test doubles taxonomy (Meszaros) and the relationship between platform fidelity, hardware modelling, and testbench capability are covered in the embedded systems testing series (article forthcoming).

Hardware-in-the-Loop

Bridging simulation to real hardware.

Commercial HIL Platforms

Tool Type Description
dSPACE SCALEXIO Commercial Platform Real-time HIL simulation for automotive ECU testing.
NI VeriStand Commercial Tool Real-time test configuration for HIL systems.
Speedgoat Commercial Platform Real-time target machines for Simulink Real-Time. One-click RCP and HIL from Simulink models.
Vector VT System Commercial Platform ECU testing with CAN/LIN/FlexRay network simulation.

Debug Interfaces

Tool Type Description
JTAG (IEEE 1149.1) Standard Protocol On-chip debug interface. Used across ARM, RISC-V, MIPS, and FPGA targets. TI Primer (free).
SWD Standard Protocol ARM Serial Wire Debug. Two-pin alternative to JTAG for Cortex-M/A/R.
Lauterbach TRACE32 Commercial Tool Debug and trace tools. Hardware trace with streaming to host.
J-Link EDU Commercial Hardware Segger debug probe (educational license). Broadest device support.
Black Magic Probe OSS Tool Debug probe with built-in GDB server. No host software needed. Can flash onto ST-Link clones.
ST-Link Commercial Hardware STMicroelectronics debug probe. Ships on Nucleo/Discovery boards. Very low cost.
LPC-Link2 Commercial Hardware NXP debug probe. Runs CMSIS-DAP or J-Link firmware.
Raspberry Pi Debug Probe OSS Tool Pico-based CMSIS-DAP probe. ~$12.
DAPLink OSS Tool ARM open source debug probe firmware (CMSIS-DAP). Runs on various boards.

USB Bus Adapters

Low-cost USB adapters for exercising target peripherals (I2C, SPI, GPIO, CAN) from a host during HIL testing.

Tool Type Description
Total Phase Aardvark Commercial Hardware USB-to-I2C/SPI host adapter. Python API. Industry standard for bus exercising.
Total Phase Beagle Commercial Hardware USB/I2C/SPI protocol analyzer. Non-intrusive monitoring.
Bus Pirate OSS Tool Open-source multi-protocol bus interface (I2C, SPI, UART, 1-Wire, JTAG).
FTDI FT2232H Commercial Hardware Dual-channel USB-to-MPSSE (I2C, SPI, JTAG, UART). Widely used in dev boards.
GreatFET OSS Tool Open-source USB peripheral for hardware hacking. GPIO, I2C, SPI, logic analysis.
CANable OSS Tool Open-source USB-to-CAN adapter. Works with SocketCAN on Linux.

Scriptable Debug Software

Tool Type Description
OpenOCD OSS Tool Open On-Chip Debugger. Bridges cheap probes to GDB for scripted test execution.
pyOCD OSS Tool Python-based debug access for ARM Cortex-M. Good for CI scripting.
probe-rs OSS Tool Rust-based embedded debugging and flashing toolkit.

Open-Source Approaches

Tool Type Description
metal.test OSS Tool GDB-based HIL: run tests on real targets via debug probe, report to CI.
Golioth HIL OSS Tool Zephyr Twister with hardware runners for on-target regression testing.

Build and Integration

Assembling simulation environments, generating code from specifications, and making it reproducible.

Build Systems

Tool Type Description
Yocto / OpenEmbedded OSS Tool Embedded Linux build system. Built-in QEMU integration via runqemu.
Buildroot OSS Tool Simple, fast embedded Linux build system. QEMU defconfigs included.
KAS OSS Tool Setup tool for Bitbake/Yocto projects. Simplifies multi-layer configuration.
FuseSoC OSS Tool Package manager and build system for HDL code.

Middleware and Transport

Tool Type Description
Eclipse Cyclone DDS OSS Library High-performance DDS implementation. Default middleware for ROS 2.
OpenSplice DDS OSS Library Vortex OpenSplice community edition (LGPL). Legacy; see Cyclone DDS.
Eclipse Zenoh OSS Library Low-latency pub/sub protocol. Used as FSS demonstrator transport layer.
Eclipse iceoryx OSS Library True zero-copy shared-memory IPC. Automotive origins (AUTOSAR Adaptive). ROS 2 transport option.
Eclipse SDV OSS Project Software Defined Vehicle project. FSS aligns with for automotive simulation.

Code Generation

The pipeline pattern — specification → parser → template → output — applies across all these tools (article forthcoming).

Tool Type Description
Jinja2 OSS Library Python template engine. Common choice for custom code generation pipelines.
svd2rust OSS Tool Generates Rust peripheral access crates from CMSIS-SVD files.
PeakRDL OSS Tool SystemRDL-based register code generation (C headers, UVM, HTML docs).
rggen OSS Tool Register generator from SystemRDL/YAML. RTL, UVM, C header output.
cheby OSS Tool CERN hardware register description tool. VHDL, Verilog, C, Python output.
development-utils OSS Tool Jinja2 generators for SVD, SystemRDL, Device Tree, DBML, IDL → C++17/C++20.

CI for Simulation

Tool Type Description
GitHub Actions + Zephyr OSS Tool Zephyr setup action for CI. Twister runs native_sim and QEMU targets.
Renode GitHub Action OSS Tool Run Renode simulation tests in CI. Robot Framework integration.
Docker containers OSS Tool Pre-built images with simulation toolchains for reproducible CI environments.

Reproducibility

Tool Type Description
Nix OSS Tool Reproducible builds and development environments. Declarative configuration.
Docker OSS Tool Container-based environment isolation for build and simulation.
Yocto reproducible builds OSS Tool Yocto’s reproducible_build class for bit-identical output.

My Repos

Simulation-related repositories, categorized by the taxonomy above.

Original

Category Sub-category Repo Description
Machine Readable Specifications ISA Specifications riscv-isa-data Machine readable RISC-V ISA data.
Machine Readable Specifications ISA Specifications riscv-docs-html HTML and machine readable metadata generated from RISC-V specs.
System Simulation Frameworks and Kernels scftgu Study material and exercises for SCFTGU 2nd Ed.
System Simulation Tracing and Debugging cpp-vcd-tracer VCD (Value Change Dump) tracing for C++.
System Simulation Tracing and Debugging riscv-gtkwave GTKWave decoders for RISC-V.
Build and Integration Code Generation development-utils Code generators, MMIO register interfaces.
Build and Integration Code Generation sifive-cxx-mmio-devices Generated C++ code for accessing SiFive peripherals.
Build and Integration Code Generation riscv-csr-access RISC-V CSR access routines.
Build and Integration CI for Simulation build-and-verify Docker containers for building and verifying RISC-V firmware.
Build and Integration Code Examples riscv-scratchpad RISC-V scratchpad.
Build and Integration Code Examples modern-cxx-riscv Baremetal RISC-V examples with modern C++.
Build and Integration Code Examples c-hardware-access-riscv Low level RISC-V hardware access with C.
Build and Integration Code Examples baremetal-cxx-coro C++20 coroutines on baremetal RISC-V.

Forked

Category Sub-category Repo Description Fork change
Machine Readable Specifications System Architecture PySysML2 SysML 2.0 textual model parser. Enum def and connection def support.
Machine Readable Specifications Interface Definitions idl_parser OMG IDL parser. OpenSplice IDL examples and parse testing.
System Simulation Simulated Processors riscv-isa-sim RISC-V Spike ISA simulator. Added VCD tracing output.
System Simulation Frameworks and Kernels SystemC Accellera SystemC reference implementation. Version history (1.0.2-2.3.2) from tarballs, enhanced Doxygen.
System Simulation Frameworks and Kernels SystemC-QuickThreads QuickThreads coroutine package from SystemC. Extracted and packaged standalone.
System Simulation Frameworks and Kernels SCFTGU_BOOK SCFTGU book exercise archive. Unzipped examples for easy access.
Build and Integration Middleware and Transport opensplice Vortex OpenSplice DDS. Javac version check fix, improved cleanup error reporting.

Detailed Topics

SystemC

SystemC is a C++ class library for system-level design and verification, spanning hardware and software. The reference implementation is now open source under Apache 2.0.

Official

Related Accellera projects: UVM-SystemC, CCI, FC4SC

Other

Historical

Before Accellera published the source on GitHub, I assembled a reference repo from the Accellera download tarballs (versions 1.0.2 through 2.3.2) for online code browsing. The Doxygen output was enhanced over the mainline: source comments were converted to doxygen format, enums and macro definitions were documented, and treeview navigation and search were added.