• RISC-V: A Bare-metal Introduction with C++. Part 7, Conclusion.

    This post is a draft for Medium. Is it possible to write pure modern C++ baremetal firmware from ground up for RISC-V? The answer is a qualified yes. The toolchain using Platform IO supported modern C++ with a small configuration change. The startup code required some assembly, but was mostly...


  • RISC-V: A Bare-metal Introduction with C++. Part 6, Interrupt Handling.

    This post is a draft for Medium. The basics of RISC-V interrupt handling, and C++ lambda functions. What are the basics of interrupt handing in RISC-V? Can we utilize modern C++ to simplify the interrupt handling? RISC-V Machine Mode Interrupts The RISC-V ISA is not specialized for embedded applications (compared...


  • RISC-V: A Bare-metal Introduction with C++. Part 5, Machine Mode Timer.

    This post is a draft for Medium. The RISC-V machine mode timer and timing keeping using the C++ std::chrono library. How does RISC-V keep time? How can we perform a periodic task with no operating system? You may take for granted that you can simply ask the operating system to...


  • RISC-V: A Bare-metal Introduction using C++. Part 4, System Registers.

    This post is a draft. What are system registers in RISC-V? How can we access them with modern C++? System registers require special instructions to access, so unlike memory mapped registers (MMIO) we can’t just cast a pointer to memory to get access them in C++. Do we need to...


  • RISC-V: A Bare-metal Introduction with C++. Part 3, Startup.

    This post is a draft for Medium. Following on from setting up the development environment in the previous post. How do we go from from reset in RISC-V to entering the main() function in C++. Startup code is generally not something you need to worry about, however it is of...