A draft for Medium. What are the foundations of designing and implementing low level software that interacts with real world systems? (By low level I mean baremetal or small footprint RTOS, on a small processor core - Not embedded Linux on a Cortex-A class MCU) An introductory embedded systems book...

This post is a draft for Medium. This is the last post in the series. Is it possible to write pure modern C++ baremetal firmware from ground up for RISC-V? The answer is a qualified yes. The toolchain using Platform IO supported modern C++ with a small configuration change. The...

This post is a draft for Medium. This is the seventh post in a series. This post is about RISC-V interrupt handling in C++. What are the basics of interrupt handing in RISC-V? Can we utilize modern C++ to simplify the interrupt handling? RISC-V Machine Mode Interrupts The RISC-V ISA...

This post is a draft for Medium. This is the sixth post in a series, about the RISC-V machine mode timer and timing keeping using the C++ std::chrono library. How does RISC-V keep time? How can we perform a periodic task with no operating system? You may take for granted...

This post is a draft for Medium. This is the fifth post in a series. What are system registers in RISC-V? How can we access them with modern C++? System registers require special instructions to access, so unlike memory mapped registers (MMIO) we can’t just cast a pointer to memory...